FIG. 16 shows the configuration of a conventional wireless communication device disclosed in JP-A No. 355198/1999.
As illustrated in FIG. 16, the device includes: a central processing unit CPU (hereinafter called the processor) 1; a frame synchronous circuit SYN (hereinafter called the synchronous circuit) 2; a receiver circuit RCV 3; a register (control means) REG 4; a switching circuit SWC 5; an oscillator OSC 6 which outputs high speed clock CK; a real time clock RTC with a timer function which is used as a clock function of the wireless communication device, RTC (hereinafter called RTC) 7; an input/output circuit I/O (hereinafter called I/O) 8; a timer TIM 9; an interruption circuit INTC 10; and a bus for receiving and transmitting addresses, data and, control data, 11.
The switching circuit SWC 5 selects either clock CK1 outputted from the oscillator OSC 6 or clock CK2 outputted from RTC 7 according to control data from the processor CPU 1 which is written and stored in the register REG 4, and supplies the selected clock to the processor CPU 1, synchronous circuit SYN 2, and register REG 4.
The timer TIM 9 operates all the time according to clock CK2 outputted from RTC 7 and in the intermittent mode (sleep mode) after paging channel reception, time to supply clock CK2 outputted from RTC 7 is set on the timer TM 9 by the processor CPU 1. As the timer TIM 9 times out, it outputs an interruption control signal to the interruption circuit INTC 10 to bring the interruption circuit INTC 10 into an interruption status.
When the interruption circuit INTC 10 receives an interruption control signal from the timer TIM 9 or an interruption request which is keyed in by the user via the I/O 8, it notifies the processor CPU 1 of occurrence of the interruption request. In other words, the interruption circuit INTC 10 outputs the interruption request to the processor CPU 1.
After a timer value is set on the timer TIM 9 by the processor CPU 1, the processor CPU 1 writes control data into the register REG 4. According to the control data stored in the register REG 4, the switching circuit SWC 5 switches clock CK1 outputted from the oscillator OSC 6 to clock CK2 outputted from RTC 7 and sends clock CK2 to the processor CPU 1, synchronous circuit SYN 2, register REG 4 and so on. In this way, the processor CPU 1, synchronous circuit SYN 2, register REG 4, and so on operate in accordance with clock CK2. Furthermore, the oscillator OSC 6 stops operating according to control data written in the register REG 4.
When the processor CPU 1 receives an interruption request from the interruption circuit INTC 10, it decides which circuit has outputted the interruption request. If it decides that the request has come from a circuit other than the timer TIM 9, it processes the request in accordance with clock CK1 and waits for arrival of a next interruption request.
If the processor CPU 1 decides that the received interruption request has come from the timer TIM 9, then it writes control data in the register REG 4. The switching circuit SWC 5 switches clock CK2 from RTC 7 to clock CK1 from the oscillator OSC 6 according to the control data written in the register REG 4. The clock CK1 thus selected is sent to the processor CPU 1, synchronous circuit SYN 2, register REG 4 and so on.
[Patent Document 1]
JP-A No. 355198/1999
Prior to filing this application, the inventor of the present invention et al reviewed the above prior art. Since wireless communication equipment includes information processing devices incorporating a function of electronic mail, a browser, an audio visual recorder/players, and the like, the inventor et al also reviewed application of the wireless communication device as disclosed in Patent Document 1 to an information processing device. When the conventional wireless communication device is used for an information processing device, a memory MEM 21 should be added to the wireless communication device as shown in FIG. 16 and the memory MEM 21 should contain an operating system OS (hereinafter called the “OS”). The OS 22 performs time supervision and management of the information processing device by making the timer TIM 9 issue an interruption request in each desired cycle.
The inventor et al have found that there are two problems to be solved regarding a cyclic interruption request from the timer TIM 9 in the information processing device which uses the wireless communication device as shown in FIG. 16 or a conventional wireless communication device.
The first problem is a phenomenon that when a cyclic interruption request is made in the standby power reduction mode, the mode is cancelled in accordance with the interruption request cycle and clock CK1 and clock CK2 are supplied to the processor CPU 1, resulting in current consumption. This phenomenon is explained below referring to FIG. 17.
FIG. 17 shows current consumption 41 of the processor CPU 1 in different operating modes. In this graph, 42 represents a timer interruption request mode and 43 a standby power reduction mode. When the OS 22 has a multi-task function, arrangements are made to insert the standby power reduction mode in the infinite loop of a lowest-priority task. In other words, it is to assume an idle state in which clock CK1 is supplied to the processor CPU 1, namely information processing is possible but not performed for a while, or laxity time before the deadline. The duration of the timer interruption request mode 42 which lasts from a timer interruption until the next timer interruption is called timer interruption duty.
If the above-mentioned lowest-priority task is started in the idle state in order to prevent wasteful current consumption, the timer TIM 9 issues an interruption request (timer interruption request mode 42) to cancel the standby power reduction mode 43, which supplies clock CK1 to the processor CPU 1 and starts the CPU 1; as a consequence, power consumption 41 increases in a situation where current consumption should be reduced. This phenomenon can be suppressed by lengthening the timer cycle 44 to decrease the number of interruption requests made by the timer 9, lengthen the standby power reduction time 43 and thus reduce current consumption 41.
However, the OS 22 performs time supervision and management while internally counting with a system clock 24 at each cyclic interruption request. Therefore, it has been found that when the timer cycle 44 of the timer TIM 9 is lengthened, time accuracy worsens in dequeuing a queued task within a time period shorter than the timer cycle 44 due to timeout. In other words, when an attempt is made to reduce current consumption 41, time accuracy worsens; and on the other hand, when an attempt is made to improve time accuracy, current consumption 41 increases.
The second problem is a phenomenon that an interruption from the timer TIM 9 which occurs in every timer cycle 44 conflicts with an interruption request from the I/O circuit 8.
Especially when time management is prioritized, namely the level of an interruption request from the timer TIM 9 is high, the interruption circuit INTC 10 first receives a cyclic interruption request from the timer TIM 9 and just after processing the request, receives an interruption request from the I/O circuit 8 to perform I/O processing. As a result, the response to interruption requests is slow.